Aldec Provides Highest Performance FPGA Solution with the Release of Active-HDL 5.1Henderson Nevada, January 21st, 2002-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today the release of Active-HDL 5.1, the fastest, most fully automated FPGA design verification tool on the market. Active-HDL 5.1 provides users with the latest design trends in the EDA industry and has been developed to provide the best support for system designers working on high-density FPGAs as well as design teams working on collaborative FPGA projects consisting of multi-million gate designs.
Active-HDL’s multi-language simulator, which allows for concurrent simulation of VHDL, Verilog and EDIF designs, has been further enhanced to become the most universal and fastest design verification platform. In addition to major speed improvements on the order of 200%, Active-HDL 5.1 also makes better use of memory, allowing very complex designs to be handled in a PC environment.
Active-HDL 5.1’s performance improvements affect all stages of design verification, including the RTL, gate and timing levels. Results were taken from 100 designs ranging from 35,000 gates up to 1.5 million gates. Active-HDL 5.1 consistently simulated faster than previous versions, even on the most complex multi-million gate designs. Since Active-HDL 5.1’s performance is supported by new feature-rich debugging tools, the overall design development productivity is more than doubled.
Active-HDL 5.1 contains over 40 industry-leading features, some of which set new standards for the industry, allowing higher design productivity with improved design quality. Some of the more advanced features include Input/Output Port Conversion in the Block Diagram Editor, which eliminates the need for the intermediary step that converts binary code to VHDL statements; Graphical Processes that allow VHDL �processes’ and Verilog �always’ statements to be placed directly on the block diagram; Post-Simulation Debug, which saves a full history of simulation results so that designers can analyze simulation results in detail at a later time; and Job Control, which allows designers to run design portions of the design in parallel rather than in serial, further expediting the design cycle.
“Because Active-HDL 5.1 provides ultra-fast simulation runtimes in a completely integrated, feature-rich environment, designers will be able to deliver designs to the market in about half the time. In order to ensure that Active-HDL 5.1 contains those features which will be of most benefit to system designers, many of the features included were suggested directly from our customer base in addition to other technologies that were proven to best benefit our customers’ designs,” stated Megan Moran, Product Marketing Manager of Active-HDL.
Active-HDL 5.1 also offers greater licensing flexibility because designers may now have the license ascribed to a USB port in addition to a traditional parallel port or floating license. The new release of Active-HDL combines ease-of-use with high power simulation to provide designers with a complete solution to FPGA designs.
Availability
Aldec is currently offering the Active-HDL environment as either a floating or node-lock license and includes Aldec’s HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered
trademarks are property of their respective owners
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Contact: Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com
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